The recent development of various forms of microprocessor units (MPU), particularly those fabricated in the form of MOS monolithic integrated circuits, has made feasible a broad new range of digital control applications and has, concurrently, introduced a number of additional constraints which must be met for the optimum system design of the stored program digital control systems which are based on the MPU. A major constraint is that the cost and complexity of the hardware and programs required to work with associated peripheral units must be minimized. In conventional systems based on stored program digital computers, the cost and complexity of the hardware required for the system to interface with a given peripheral unit is usually a minor consideration when compared with the cost of the main system. Systems based on the use of intergrated circuit microprocessors, however, are much lower in cost because of the economy of integrated circuit fabrication. In systems where an MPU is used to control a large number of peripherals, cost of the hardware, complexity of the interconnecting wiring and the quantity of memory required for program storage are often the dominant constraints. Further, in systems where an MPU is used to control high speed peripherals such as high speed serial memory units via appropriate system interface chips, the amount of MPU "overhead" time, that is the time required by the MPU for performing system functions not related to the peripheral, becomes a dominant constraint.
In MPU based digital systems for relatively low speed serial data applications, an "interrupt driven" mode of system organization is often used. In a typical microprocessor system, each interrupt request generated by a system peripheral would require that internally the MPU would store critical internal register states to enable it to proceed with assigned programming tasks once the interrupt request has been serviced. Typically this process of saving the contents of internal registers could take anywhere from 12 to 24 microseconds. Thus in a low speed serial data system, the amount of time required to service an interrupt request is short relative to the amount of time required to process a single byte of serial data. It follows therefore that the efficient system operation can be obtained by designing the peripheral unit to generate an interrupt request to the microprocessor unit each time a new byte of serial data arrives or when the peripheral unit is available for data transmission.
In MPU-based systems controlling serial data transfer at higher speeds, a "polled" mode of system operation is often used. In this mode of operation, the system program is arranged to interrogate the particular peripheral units dedicated to providing high speed serial data interface at predetermined time intervals. These time intervals are chosen to be short enough so that interrogation and the associated receiving of a byte of data will be accomplished before the next serial byte of data arrives. In such system, interrogation by the controlling MPU usually begins with status checking which verifies internal states within the given peripheral unit. This checking verifies that no data transfer errors such as parity errors or errors due to underflow or overflow have occurred. As serial data transfer rates increase above 250,000 bits per second, MPU-based systems become limited by program execution time even when the systems are designed for a polled mode of operation. Thus it has been difficult to provide efficient and reliable MPU-based data systems for controlling popular new peripheral devices such as flexible disk (floppy disk) memory units.